741 operational amplifier

An operational amplifier (often op-amp or opamp) is a DC-coupled high-gain electronic voltage amplifier with a differential input and, usually, a single-ended output.^[1] In this configuration, an op-amp produces an output potential (relative to circuit ground) that is typically hundreds of thousands of times larger than the potential difference between its input terminals. Operational amplifiers had their origins in analog computers, where they were used to perform mathematical operations in many linear, non-linear and frequency-dependent circuits. The popularity of the op-amp as a building block in analog circuits is due to its versatility. Due to negative feedback, the characteristics of an op-amp circuit, its gain, input and output impedance, bandwidth etc. are determined by external components and have little dependence on temperature coefficients or manufacturing variations in the op-amp itself.

Operation[edit]

An op-amp without negative feedback (a comparator)

The amplifier's differential inputs consist of a non-inverting input (+) with voltage V₊ and an inverting input (–) with voltage V₋; ideally the op-amp amplifies only the difference in voltage between the two, which is called the differential input voltage. The output voltage of the op-amp V_out is given by the equation

${\displaystyle V_{\text{out}}=A_{\text{OL}}(V_{+}-V_{-}),}$

where A_OL is the open-loop gain of the amplifier (the term "open-loop" refers to the absence of a feedback loop from the output to the input).

Open-loop amplifier[edit]

The magnitude of A_OL is typically very large (100,000 or more for integrated circuit op-amps), and therefore even a quite small difference between V₊ and V₋ drives the amplifier output nearly to the supply voltage. Situations in which the output voltage is equal to or greater than the supply voltage are referred to as saturation of the amplifier. The magnitude of A_OL is not well controlled by the manufacturing process, and so it is impractical to use an open-loop amplifier as a stand-alone differential amplifier.

Without negative feedback, and perhaps with positive feedback for regeneration, an op-amp acts as a comparator. If the inverting input is held at ground (0 V) directly or by a resistor R_g, and the input voltage V_in applied to the non-inverting input is positive, the output will be maximum positive; if V_in is negative, the output will be maximum negative. Since there is no feedback from the output to either input, this is an open-loop circuit acting as a comparator.

Closed-loop amplifier[edit]

An op-amp with negative feedback (a non-inverting amplifier)

If predictable operation is desired, negative feedback is used, by applying a portion of the output voltage to the inverting input. The closed-loop feedback greatly reduces the gain of the circuit. When negative feedback is used, the circuit's overall gain and response becomes determined mostly by the feedback network, rather than by the op-amp characteristics. If the feedback network is made of components with values small relative to the op amp's input impedance, the value of the op-amp's open-loop response A_OL does not seriously affect the circuit's performance. The response of the op-amp circuit with its input, output, and feedback circuits to an input is characterized mathematically by a transfer function; designing an op-amp circuit to have a desired transfer function is in the realm of electrical engineering. The transfer functions are important in most applications of op-amps, such as in analog computers. High input impedance at the input terminals and low output impedance at the output terminal(s) are particularly useful features of an op-amp.

In the non-inverting amplifier on the right, the presence of negative feedback via the voltage divider R_f, R_g determines the closed-loop gainA_CL = V_out / V_in. Equilibrium will be established when V_out is just sufficient to "reach around and pull" the inverting input to the same voltage as V_in. The voltage gain of the entire circuit is thus 1 + R_f/R_g. As a simple example, if V_in = 1 V and R_f = R_g, V_out will be 2 V, exactly the amount required to keep V₋ at 1 V. Because of the feedback provided by the R_f, R_g network, this is a closed-loop circuit.

Another way to analyze this circuit proceeds by making the following (usually valid) assumptions:^[3]

• When an op-amp operates in linear (i.e., not saturated) mode, the difference in voltage between the non-inverting (+) pin and the inverting (−) pin is negligibly small.
• The input impedance between (+) and (−) pins is much larger than other resistances in the circuit.

The input signal V_in appears at both (+) and (−) pins, resulting in a current i through R_g equal to V_in/R_g:

${\displaystyle i={\frac {V_{\text{in}}}{R_{g}}}.}$

Since Kirchhoff's current law states that the same current must leave a node as enter it, and since the impedance into the (−) pin is near infinity, we can assume practically all of the same current i flows through R_f, creating an output voltage

${\displaystyle V_{\text{out}}=V_{\text{in}}+i\times R_{f}=V_{\text{in}}+\left({\frac {V_{\text{in}}}{R_{g}}}\times R_{f}\right)=V_{\text{in}}+{\frac {V_{\text{in}}\times R_{f}}{R_{g}}}=V_{\text{in}}\left(1+{\frac {R_{f}}{R_{g}}}\right).}$

By combining terms, we determine the closed-loop gain A_CL:

${\displaystyle A_{\text{CL}}={\frac {V_{\text{out}}}{V_{\text{in}}}}=1+{\frac {R_{f}}{R_{g}}}.}$

Op-amp characteristics[edit]

Ideal op-amps[edit]

An equivalent circuit of an operational amplifier that models some resistive non-ideal parameters.

An ideal op-amp is usually considered to have the following characteristics:^[4][5]

• Infinite open-loop gain G = v_out / v_in
• Infinite input impedance R_in, and so zero input current
• Zero input offset voltage
• Infinite output voltage range
• Infinite bandwidth with zero phase shift and infinite slew rate
• Zero output impedance R_out
• Zero noise
• Infinite common-mode rejection ratio (CMRR)
• Infinite power supply rejection ratio.

These ideals can be summarized by the two "golden rules":

1. In a closed loop the output attempts to do whatever is necessary to make the voltage difference between the inputs zero.
2. The inputs draw no current.^[6]:177

The first rule only applies in the usual case where the op-amp is used in a closed-loop design (negative feedback, where there is a signal path of some sort feeding back from the output to the inverting input). These rules are commonly used as a good first approximation for analyzing or designing op-amp circuits.^[6]:177

None of these ideals can be perfectly realized. A real op-amp may be modeled with non-infinite or non-zero parameters using equivalent resistors and capacitors in the op-amp model. The designer can then include these effects into the overall performance of the final circuit. Some parameters may turn out to have negligible effect on the final design while others represent actual limitations of the final performance that must be evaluated.

TIMER IC 555

TIMER IC 555

The 555 timer IC is an integrated circuit (chip) used in a variety of timer, pulse generation, and oscillator applications. The 555 can be used to provide time delays, as an oscillator, and as a flip-flop element. Derivatives provide two or four timing circuits in one package.

Introduced in 1972^[1] by Signetics,^[2] the 555 is still in widespread use due to its low price, ease of use, and stability. It is now made by many companies in the original bipolar and in low-power CMOS. As of 2003, it was estimated that 1 billion units were manufactured every year.^[3] The 555 is the most popular integrated circuit ever manufactured

HISTORY:

The IC was designed in 1971 by Hans R. Camenzind under contract to Signetics (later acquired by Philips Semiconductors, and now NXP).

In 1962, Camenzind joined PR Mallory's Laboratory for Physical Science in Burlington, Massachusetts.^[3] He designed a pulse-width modulation (PWM) amplifier for audio applications,^[6] but it was not successful in the market because there was no power transistor included. He became interested in tuners such as a gyrator and a phase-locked loop (PLL). He was hired by Signetics to develop a PLL IC in 1968. He designed an oscillator for PLLs such that the frequency did not depend on the power supply voltage or temperature. However, Signetics laid off half of its employees, and the development was frozen due to a recession.^[7]

Camenzind proposed the development of a universal circuit based on the oscillator for PLLs, and asked that he would develop it alone, borrowing their equipment instead of having his pay cut in half. Other engineers argued the product could be built from existing parts, but the marketing manager bought the idea. Among 5xx numbers that were assigned for analogue ICs, the special number "555" was chosen.^[3][7]

Camenzind also taught circuit design at his nearby university^[which?] in the morning, and went to the Northeastern University to get the master's degree at night. The first design was reviewed in the summer of 1971. There was no problem, so it had gone to the layout design. A few days later, he got the idea of using a direct resistance instead of a constant current source, and found that it worked. The change decreased the required 9 pins to 8, so the IC could be fit in an 8-pin package instead of a 14-pin package. This design passed the second design review, and the prototype was completed in October 1971. Its 9-pin copy had been already released by another company founded by an engineer who attended the first review and retired from Signetics, but they withdrew it soon after the 555 was released. The 555 timer was manufactured by 12 companies in 1972 and it became the best selling product.

Design

Internal schematic (bipolar version)

Internal schematic (CMOS version)

Depending on the manufacturer, the standard 555 package includes 25 transistors, 2 diodes and 15 resistors on a silicon chip installed in an 8-pin mini dual-in-line package (DIP-8).^[8] Variants available include the 556 (a 14-pin DIP combining two 555s on one chip), and the two 558 & 559s (both a 16-pin DIP combining four slightly modified 555s with DIS & THR connected internally, and TR is falling edge sensitive instead of level sensitive).

The NE555 parts were commercial temperature range, 0 °C to +70 °C, and the SE555 part number designated the military temperature range, −55 °C to +125 °C. These were available in both high-reliability metal can (T package) and inexpensive epoxy plastic (V package) packages. Thus the full part numbers were NE555V, NE555T, SE555V, and SE555T. It has been hypothesized that the 555 got its name from the three 5 kΩ resistors used within,^[9] but Hans Camenzind has stated that the number was arbitrary.^[3]

Low-power versions of the 555 are also available, such as the 7555 and CMOS TLC555.^[10] The 7555 is designed to cause less supply noise than the classic 555 and the manufacturer claims that it usually does not require a "control" capacitor and in many cases does not require a decoupling capacitor on the power supply. Those parts should generally be included, however, because noise produced by the timer or variation in power supply voltage might interfere with other parts of a circuit or influence its threshold voltages.

Pins[edit]

Pinout diagram

The connection of the pins for a DIP package is as follows:

Pin	Name	Purpose
1	GND	Ground reference voltage, low level (0 V)
2	TRIG	The OUT pin goes high and a timing interval starts when this input falls below 1/2 of CTRL voltage (which is typically 1/3 VCC, CTRL being 2/3 VCC by default if CTRL is left open). More simply we can say that OUT will be high as long as the trigger is kept at low voltage. Output of the timer totally depends upon the amplitude of the external trigger voltage applied to this pin.
3	OUT	This output is driven to approximately 1.7 V below +VCC, or to GND.
4	RESET	A timing interval may be reset by driving this input to GND, but the timing does not begin again until RESET rises above approximately 0.7 volts. Overrides TRIG which overrides THR. (THR instead overrides TRIG on the LM555)
5	CTRL	Provides "control" access to the internal voltage divider (by default, 2/3 VCC).
6	THR	The timing (OUT high) interval ends when the voltage at THR ("threshold") is greater than that at CTRL (2/3 VCC if CTRL is open). Overrides TRIG on the LM555
7	DIS	Open collector output which may discharge a capacitor between intervals. In phase with output.
8	VCC	Positive supply voltage, which is usually between 3 and 15 V depending on the variation.

Pin 5 is also sometimes called the CONTROL VOLTAGE pin. By applying a voltage to the CONTROL VOLTAGE input one can alter the timing characteristics of the device. In most applications, the CONTROL VOLTAGE input is not used. It is usual to connect a 10 nF capacitor between pin 5 and 0 V to prevent interference. The CONTROL VOLTAGE input can be used to build an astable multivibrator with a frequency-modulated output.

Modes

The IC 555 has three operating modes:

1. Bistable mode or Schmitt trigger – the 555 can operate as a flip-flop, if the DIS pin is not connected and no capacitor is used. Uses include bounce-free latched switches.
2. Monostable mode – in this mode, the 555 functions as a "one-shot" pulse generator. Applications include timers, missing pulse detection, bounce-free switches, touch switches, frequency divider, capacitance measurement, pulse-width modulation (PWM) and so on.
3. Astable (free-running) mode – the 555 can operate as an electronic oscillator. Uses include LED and lamp flashers, pulse generation, logic clocks, tone generation, security alarms, pulse position modulation and so on. The 555 can be used as a simple ADC, converting an analog value to a pulse length (e.g., selecting a thermistor as timing resistor allows the use of the 555 in a temperature sensor and the period of the output pulse is determined by the temperature). The use of a microprocessor-based circuit can then convert the pulse period to temperature, linearize it and even provide calibration means.

Bistable

Schematic of a 555 in bistable mode

In bistable (also called Schmitt trigger) mode, the 555 timer acts as a basic flip-flop. The trigger and reset inputs (pins 2 and 4 respectively on a 555) are held high via pull-up resistors while the threshold input (pin 6) is simply floating. Thus configured, pulling the trigger momentarily to ground acts as a 'set' and transitions the output pin (pin 3) to Vcc (high state). Pulling the reset input to ground acts as a 'reset' and transitions the output pin to ground (low state). No timing capacitors are required in a bistable configuration. Pin 5 (control voltage) is connected to ground via a small-value capacitor (usually 0.01 to 0.1 μF). Pin 7 (discharge) is left unconnected, or may be used as an open-collector output.^[11]

Monostable

Schematic of a 555 in monostable mode

The output pulse ends when the voltage on the capacitor equals 2/3 of the supply voltage. The output pulse width can be lengthened or shortened to the need of the specific application by adjusting the values of R and C.^[12]

The output pulse width of time t, which is the time it takes to charge C to 2/3 of the supply voltage, is given by

${\displaystyle t=\ln(3)\cdot RC\approx 1.1RC}$

where t is in seconds, R is in ohms (resistance) and C is in farads (capacitance).

While using the timer IC in monostable mode, the main disadvantage is that the time span between any two triggering pulses must be greater than the RC time constant.^[13] Conversely, ignoring closely spaced pulses is done by setting the RC time constant to be larger than the span between spurious triggers. (Example: ignoring switch contact bouncing.)

Astable

Schematic of a 555 in astable mode

In astable mode, the 555 timer puts out a continuous stream of rectangular pulses having a specified frequency. Resistor R₁ is connected between V_CC and the discharge pin (pin 7) and another resistor (R₂) is connected between the discharge pin (pin 7), and the trigger (pin 2) and threshold (pin 6) pins that share a common node. Hence the capacitor is charged through R₁ and R₂, and discharged only through R₂, since pin 7 has low impedance to ground during output low intervals of the cycle, therefore discharging the capacitor.

In the astable mode, the frequency of the pulse stream depends on the values of R₁, R₂ and C:

${\displaystyle f={\frac {1}{\ln(2)\cdot C\cdot (R_{1}+2R_{2})}}}$^[14]

The high time from each pulse is given by:

${\displaystyle \mathrm {high} =\ln(2)\cdot C\cdot (R_{1}+R_{2})}$

and the low time from each pulse is given by:

${\displaystyle \mathrm {low} =\ln(2)\cdot C\cdot R_{2}}$

where R₁ and R₂ are the values of the resistors in ohms and C is the value of the capacitor in farads.

The power capability of R₁ must be greater than ${\displaystyle {\frac {V_{cc}^{2}}{R_{1}}}}$.

Particularly with bipolar 555s, low values of ${\displaystyle R_{1}}$ must be avoided so that the output stays saturated near zero volts during discharge, as assumed by the above equation. Otherwise the output low time will be greater than calculated above. The first cycle will take appreciably longer than the calculated time, as the capacitor must charge from 0V to 2/3 of V_CC from power-up, but only from 1/3 of V_CC to 2/3 of V_CC on subsequent cycles.

To have an output high time shorter than the low time (i.e., a duty cycle less than 50%) a small diode (that is fast enough for the application) can be placed in parallel with R₂, with the cathode on the capacitor side. This bypasses R₂ during the high part of the cycle so that the high interval depends only on R₁ and C, with an adjustment based the voltage drop across the diode. The voltage drop across the diode slows charging on the capacitor so that the high time is a longer than the expected and often-cited ln(2)*R₁C = 0.693 R₁C. The low time will be the same as above, 0.693 R₂C. With the bypass diode, the high time is

${\displaystyle \mathrm {high} =R_{1}\cdot C\cdot \ln \left({\frac {2V_{\textrm {cc}}-3V_{\textrm {diode}}}{V_{\textrm {cc}}-3V_{\textrm {diode}}}}\right)}$

where V_diode is when the diode's "on" current is 1/2 of V_cc/R₁ which can be determined from its datasheet or by testing. As an extreme example, when V_cc= 5 and V_diode= 0.7, high time = 1.00 R₁C which is 45% longer than the "expected" 0.693 R₁C. At the other extreme, when V_cc= 15 and V_diode= 0.3, the high time = 0.725 R₁C which is closer to the expected 0.693 R₁C. The equation reduces to the expected 0.693 R₁C if V_diode= 0.

The operation of RESET in this mode is not well-defined. Some manufacturers' parts will hold the output state to what it was when RESET is taken low, others will send the output either high or low.

The astable configuration, with two resistors, cannot produce a 50% duty cycle. To produce a 50% duty cycle, eliminate R1, disconnect pin 7 and connect the supply end of R2 to pin 3, the output pin. This circuit is similar to using an inverter gate as an oscillator, but with fewer components than the astable configuration, and a much higher power output than a TTL or CMOS gate. The duty cycle for either the 555 or inverter-gate timer will not be precisely 50% and will change based off any load that the output is also driving while high (longer duty cycles for greater loads) due to the fact the timing network is supplied from the devices output pin, which has different internal resistances depending on whether it is in the high or low state (high side drivers tend to be more resistive).

Specifications

These specifications apply to the NE555. Other 555 timers can have different specifications depending on the grade (military, medical, etc.).

Supply voltage (VCC)	4.5 to 15 V
Supply current (VCC = +5 V)	3 to 6 mA
Supply current (VCC = +15 V)	10 to 15 mA
Output current (maximum)	200 mA
Maximum Power dissipation	600 mW
Power consumption (minimum operating)	30 mW@5V, 225 mW@15V
Operating temperature	0 to 75 °C